1. Field of the Invention
The present invention relates to a semiconductor memory operating in synchronization with an external clock signal.
2. Description of the Related Art
Recent high-speed microprocessors require high-speed semiconductor memory, in particular, high-speed static random access memory (SRAM) serving as cache memory. High-speed data transfer between such microprocessors and cache memory takes place at precision timing, and therefore, imposes severe demands on the specifications of skews involved in data output from the memory.
Memory is tested with testers before shipment. The accuracy of the testers is becoming hard to keep pace with the extreme specifications of recent memory. It is difficult for the existing testers to measure the data skews involved in recent memory.
To cope with this problem, Harold Pilo, et al., “DESIGN-FOR-TEST METHODS FOR STAND-ALONE SRAMS AT 1 Gb/s/pin AND BEYOND”, International Test Conference 2000 Proceedings, pp. 436-443 has proposed to install a data skew measuring circuit into memory. As shown in FIG. 1, the memory employing such a data skew measuring circuit has a memory core 70 including buffers 71, registers 72, and a memory array 73. Data DQ, an address A, and a command CMD are retrieved and stored in the registers 72 through the buffers 71 in synchronization with a clock signal CK. From the registers 72, the data pieces are transferred to the memory array 73. The data and clock signal are also stored in registers 80 (80a to 80n) in response to a strobe signal STRB generated at predetermined timing. Although the data DQ shown in FIG. 1 is simplified, real data DQ involves a data width of a plurality of bits, which are stored in the registers 80, respectively. The memory includes a boundary scan circuit 90 (IEEE 1149.1). The data pieces stored in the registers 80 are serially read and output through a boundary scan chain of the circuit 90. For example, a data piece held in the register 80m is selected by a selector 91m and is stored in a register 92m. The data piece in the register 92m is transferred to a next register 92n through a selector 91n, and then, is sequentially output through a buffer 93. The circuit 90 is effective in suppressing the chip area of the memory.
FIGS. 2A to 2C show the operation of the circuit 90 when measuring data skews. Two data pieces DQ1 and DQ2 are shown in FIGS. 2A to 2C as examples. The data piece DQ1 is supplied to the register 80m and the data piece DQ2 to the register 80n. Rise timing of the strobe signal STRB is successively swept, and at a rise of the strobe signal STRB, it is checked to see whether data in each register 80 is 0 or 1. Based on results of the checking of the registers 80, skew between the data pieces DQ1 and DQ2 is measured. The strobe signal STRB is shifted step by step. The length of each shifting step can sufficiently be shortened even with a standard tester, and therefore, even the standard tester can measure such a data skew. The “shifting step” is the length of an arrow mark B of FIG. 2B, or the difference between the length of an arrow mark C of FIG. 2C and that of the arrow mark B of FIG. 2B. In addition to data, the clock signal CK can be held in one of the registers 80, to measure the time (access time) between the rise of the clock signal and the data output.
The related art mentioned above has some problems. Data pieces such as DQ1 and DQ2 of FIG. 2 involve different rise timings in different clock cycles (operating cycles). The related art, however, measures data skews in only a single operating cycle. It is difficult for the related art to measure data skews in a plurality of operating cycles and find a worst valid time or a worst invalid time.